It is well known that noise generated by radiation such as alpha rays or neutrons causes generation of an error in a memory circuit, e.g., a register or a memory cell in a hardware circuit.
Therefore, such a technology is well known that data is protected from an error by providing parity check or error-check-and-correct (ECC) or other methods to a memory circuit upon designing the hardware circuit.
It cannot be verified by simulation, whether or not these functions work fine. Consequently, the verification is required by actually generating an error.
Then, such a technology is well-known that a circuit (error generating circuit) for generating an error is arranged to a memory circuit that is protected from the error so as to perform logic verification.
In addition, such a technology is well known that an adapter is inserted between a memory control circuit and a memory unit, and a data error designated by the adapter is inserted and is written to the memory unit so as to inspect an error detecting/correcting function of a memory control circuit upon reading the data. Above technology is disclosed in Japanese Laid-open Patent Publication No. 2-90334 and Japanese Laid-open Patent Publication No. 2004-21922 or the like.